The present invention may relate to a digital-to-analog converter (DAC), and may be directed to reducing a settling time of an analog output from the DAC. The invention may be suitable for implementation in an integrated circuit.
When an analog output from a DAC changes, the change is not instantaneous but takes a certain time for the output to stabilize. The settling time is the time for the analog output to stabilize to within a certain tolerance, or margin, for example, to within a certain percentage of the final output value.
FIG. 1 depicts schematically a conventional integrated circuit DAC 10, and parasitic impedances at the analog output which increase the settling time undesirably. The DAC 10 includes a semiconductor die 12 including an arrangement of current sources 14 whose outputs are summed. The summed output current (i.e., IS) passes through a leadwire 16, or a leadwire network, to a pin 18 of an integrated circuit package. 17. An analog voltage is developed in a circuit 20 external to the integrated circuit DAC 10 by passing the current through a load resistor 22. The current sources 14 are controlled simultaneously so that, when the output current changes, the current sources produce a substantial step change in IS.
For low current applications, the effect of a parasitic capacitance 24 limits a slew rate of the generated analog voltage. The parasitic capacitance 24 includes the output capacitance of the DAC 10, and capacitances of the external circuit 20. Referring to FIG. 2, the parasitic capacitance slows the rate at which a current (i.e., IL) in the load resistor 22 can change. For a step change in IS, the change in IL takes the form of an exponential change, defined by an RC time constant where R is the value of the load resistor 22 and C is the value of the parasitic capacitance 24. For low current applications, a high value of the load resistor 24 is often used to enable a reasonable voltage to be developed despite the low current. However, a high load resistor 24 increases the RC time constant, and hence the settling time, undesirably.
For high frequency applications having rapid changes, a higher current is often used to enable the value of the load resistor 24 (and thus the RC time constant) to be reduced. However, for high current applications, a parasitic inductance 26 resulting from the leadwire 16 becomes significant. The parasitic inductance 26, coupled with the parasitic capacitance 24, forms a resonant circuit which creates ringing in the output current IL. Referring to FIG. 3, for a step change in IS, the change in IL takes the form of an exponentially decreasing ringing superimposed on the exponential change of FIG. 2. The magnitude of the ringing can often be as much as several bits of the DAC resolution. The settling time is adversely affected, because the output IL does not stabilise until the ringing has decayed.
The invention may relate to a digital to analog converter. The digital to analog converter may comprise a plurality of controllable current sources and a control circuit. The plurality of controllable current sources may include a first and a second controllable current source. Each of the plurality of controllable current sources may be controllable between a first state and a second state. The control circuit may be coupled to the plurality of controllable current sources. The control circuit may be configured to control digital to analog conversion at sampling intervals. The control circuit may be configured to control a first state transition of the first controllable current source at a timing in the sampling interval different from a second state transition of the second controllable current source.